Conventional Gigabit Ethernet switches use a Gigabit media independent interface (GMII) to link media access control (MAC) and physical layer (PHY) devices. GMII is a parallel interface that includes traces that run simultaneously at a fixed frequency between the paired MAC and PHY devices. The GMII interface works well for Gigabit Ethernet switches with one port or with relatively few ports. When additional ports are added, problems may arise relating to the relatively high number of pins, synchronization, cost and interference.
A reduced GMII (RGMII) decreased the number of pins by increasing the data frequency. The lower number of pins reduced the cost. However, running more energy through each trace increased the likelihood of interference. A serial gigabit interface was developed to solve problems associated with the GMII and RGMII parallel interfaces. One version of serial gigabit interface employs eight pins per port, which are allocated to four channels. Pairs are used for the receive (Rx) data, Rx clock, transmit (Tx) data, and Tx clock. The serial gigabit interface employs a low voltage differential swing (LVDS) format.
While parallel connections allow high data rates over short distances, serial links permit longer connections and reduce synchronization issues. Despite having a higher transmit frequency, interference is not as problematic because the signals do not travel in synch. Another version of the serial gigabit interface embeds the clock signal within the data channel and further reduces the number of pins per port to 4. The pins support two data streams, Rx and Tx, each with a single pair of pins. One pin in each pair is dedicated to the signals moving from the MAC device to the PHY device. Another pin is dedicated to traffic moving in the opposite direction, from the PHY device to the MAC device. This format also typically uses the LVDS format. The serial gigabit interface format also allows serializer/deserializer (SERDES) components to be integrated on the same chip.
Referring now to FIG. 1, a network device 10 includes a MAC device 12, which includes a gigabit MAC 14 and a physical coding sublayer (PCS) device 16, which implements IEEE section 802.3z, which is hereby incorporated by reference in its entirety. An output of the MAC device 12 is input to a first SERDES 20, which provides a serial link at a fixed data rate. A second SERDES 22 communicates with the first SERDES 20 and is connected to a PCS 26 of a PHY device 28 that includes a PHY 30. The PHY 30 communicates with a medium 34. The PCS 16 may perform 8/10 bit encoding as specified by 802.3z, which increases the data rate to 1.25 Gb/s. A serial management interface 36 provides control information between the MAC and the PHY, as specified by IEEE 802.3z. Because the first and second SERDES 20 and 22 must operate at 1.25 Gb/s, problems are encountered when the MAC 14 operates at lower data rates such as 10 or 100 Mb/s.
Referring now to FIG. 2, an exemplary network device 50 such as switch or a router includes a multi-port PHY device 52 and a multi-port MAC device 54. The PHY devices 52-1, 52-2, 52-3, . . . , and 52-N communicate with mediums 56-1, 56-2, 56-3, . . . , and 56-N. For example, the medium 56-1 may be copper operating according to 10BASE-T. The medium 56-2 may be copper operating according to 100BASE-TX. The medium 56-3 may be copper operating according to 1000BASE-T.
The MAC device 54 includes 10/100/1000 MAC devices 54-1, 54-2, . . . , and 54-N, which are connected by data translators 58-1, 58-2, 58-3, . . . 58-N and physical coding sublayer (PCS) devices 60-1, 60-2, . . . , and 60-N (collectively referred to as PCS device 60) to SERDES 62-1, 62-2, . . . , and 62-N (collectively referred to as SERDES 62). The SERDES 62-1, 62-2, . . . , and 62-N communicate with SERDES 64-1, 64-2, . . . , and 64-N (collectively referred to as SERDES 64) that are associated with the PHY devices 52. The SERDES 64-1, 64-2, . . . , and 64-N are connected by PCS devices 66-1, 66-2, . . . , and 66-N (collectively referred to as PCS device 66) and data translators 67-1, 67-2, . . . , 67-N to PHY devices 52-1, 52-2, . . . , and 52-N. In some implementations, the PCS devices 60 and 66 perform 8/10 bit encoding and operate in accordance with IEEE section 802.3z.
Referring now to FIGS. 2, 3A and 3B, the PHY device 52 and the MAC device 54 operate using the serial gigabit interface. Control and data bytes are passed serially. Since the data rates can be 10 Mb/s (10BASE-T), 100 Mb/s (100BASE-T) and 1000 Mb/s (1000BASE-T), the 10BASE-T and 100BASE-T rates are adjusted to 1000 Mb/s to provide a common data rate for the SERDES 62 and 64. Therefore, the data translator 58 duplicates the data at 10 Mb/s 100 times and the data at 100 Mb/s 10 times. The reverse process is performed by the translator 67. The data at 1000 Mb/s is not altered by the data translators 58 and 67.
In 10 Mb/s and 100 Mb/s modes, data is typically packaged in nibbles. Prior to replicating the data, a combiner 69 combines two adjacent nibbles into a byte. A byte duplicator 70 duplicates bytes 10 times when receiving 100 Mb/s data streams and 100 times when receiving 10 Mb/s data streams. The output of the duplicator 70 is a Gigabit Media Independent Interface (GMII) data stream that is input to an encoder 71. The encoder 71 may perform 8/10 bit encoding. The encoder 71 receives the bytes from the duplicator 30 and outputs a 1000BASE-X data stream.
Going in the reverse direction, a bit decoder 75 receives the 1000-BASE-X data stream from the SERDES 62. The decoder 75 outputs a GMII data stream to a sampler 76. The sampler 76 samples 1 out of 10 bytes for 100 Mb/s and 1 out of 100 bytes for 10 Mb/s. A byte separator 77 separates the bytes into nibbles. The serial gigabit interface uses a modified form of 1000BASE-X autonegotiation to pass speed, link, and duplex information.